The present invention relates to an address translation device for a computer system employing a multiple virtual storage method and a method for managing address information when an interrupt is brought about during the address translation performed by the device.
The multiple virtual storage method is designed to manage virtual spaces using the address translation device and a plurality of address translation tables. The method is a well-known technique used in the current mainframe. The address translation device is designed to load instructions and data on a virtual space and translate an address on the virtual space referred to as a virtual address into a real address. The method takes the step of reading data or executing instructions based on the real addresses given by the device. An operating system (OS) is provided to prepare one address translation table for one virtual space used by the address translation device and switch the address translation table for managing a plurality of virtual spaces.
The address translation method and the managing method for virtual storage are well-known techniques in a field of a mainframe. These methods are detailed in "Virtual Memory System": Hirofumi Yosizawa, "Practical Use of Operating System", Shoukoudou, Ltd., (ISBN 4-7856-3503-7), Chapter 3, pp. 85 to 124 and "Memory Management": S. E. Madnick, J. J. Donovan, "Operating Systems" McGRAW-HILL KOGAKUSYA, LTD., 07-85467-X, Chapter 3, pp. 105 to 208.
The operating system employing the multiple virtual storage method is capable of creating a plurality of virtual spaces. That is, by allocating respective virtual spaces to the users, they can use their respective allocated virtual spaces. This operating system, however, has a shortcoming that the virtual area referred by each user is limited. That is because, in actuality, each user can refer to only one virtual space and the total capacity for each user is limited by an address width specified by an instruction operand. For example, if the address width is 31 bits, the capacity is limited as 2GB (2.sup.31 B).
In order to overcome the shortcoming, an address translation device is designed to provide a space selector device for determining which virtual space an operand is to be picked up. It is disclosed in JP-A-56-140576 and 57-143783. The devices disclosed in both publications are designed to enter a base register number into a space selector device and selecting the virtual space according to the base register number. The design makes it possible to access any virtual space even if it does not contain an instruction. It results in being able to access a large capacity of virtual storage as if an address width would be substantially expanded. Concretely, these devices are designed to match a register referred to as an access register to each general-purpose register so that the access register can directly or indirectly point to a segment table. When calculating an instruction operand address, the address translation is carried out using the segment table pointed by the access register. As stated above, the access register is related to the general-purpose register specified as a base register.
This method makes it possible for a user to refer to a plurality of virtual spaces based on one virtual space by using a plurality of access registers. The difference between the inventions disclosed in JP-A-56-140576 and JP-A-57-143783 is that the former invention is designed to allow the access register to directly point to the segment table register, while the latter invention is designed to allow the access register to point to the origin register of the segment table. The difference is essentially negligible.
The address translation device described in the foregoing Laid-Open publication makes it possible for a user to refer to a plurality of virtual spaces based on one address space, thereby realizing substantial address expansion.
The address translation device disclosed in the foregoing Laid-Open publication has an object of assuming a plurality of virtual spaces for data to be accessed. On the other hand, a method is designed to locate instructions on a plurality of virtual spaces. The system is detailed, for example, in IBM manual, IBM Enterprise Systems Architecture/370, Principles of Operation, SA22-7200-0, pp. 3-1 to 3-39. Herein, a plurality of control registers have respective virtual space identifiers. And, in a special control register PSW (Program Status Word) representing the status of a processor, a flag is provided for indicating which control register is effective. Then, an instruction is read from the virtual space indicated by the control register for the specified flag and is executed. Hence, by changing the contents of the plurality of control registers and the flag contained in the PSW, it is possible to execute the instruction located on any virtual space.
The computer system employing the foregoing hardware architecture is, for example, MVS/ESA manufactured by IBM. The system prepares three spaces (primary, secondary, home) for each user for the purpose of executing the process. The home space includes basic table and program groups for managing each user. The primary and secondary spaces are designed to be freely set by each user. As such, each user can execute a program (instruction) in more than one program as well as access more than one virtual space using an access register.
As is understood from the above description, the MVS/ESA system is capable of locating an instruction on more than one virtual space and data on the other virtual spaces, thereby implementing the use of the virtual storage having a far larger capacity than the conventional 2GB capacity. The summary of the MVS/ESA system is disclosed in IBM Systems Journal, vol. 28, no. 1, pp. 15 to 61.
However, the foregoing Patent Laid-open publication, Manual and Publication disclosing the address translation methods have mentioned no functions entailed when the address translation mechanism is built in the computer system. In particular, they have mentioned no concrete mechanism or method for performing interrupt processing when a user refers to a virtual space using an access register and for managing the virtual storage and real storage based on the OS.
In general, if something disadvantageous such as an address translation exception occurs when a user program is executed, an interrupt is caused, resulting in the OS starting the interrupt processing. The architecture used in the IBM 370 series, for example, is designed to save the program status word (PSW) used when interrupt is caused in a specific address of the main storage (interrupt new PSW) and replace the PSW with the interrupt new PSW when the interrupt is caused. The interrupt new PSW can be set for each interrupt kind. Hence, by writing a program address of the OS processing interrupt to a new PSW according to each interrupt kind, it is possible to pass control to the corresponding interrupt-processing program when the interrupt is caused.
However, the information specified to the interrupt new PSW merely includes an address of an instruction to be executed when an interrupt occurs and a specification flag of a virtual space to which the instruction is read. The other control registers and access registers used when the interrupt occurs remain unchanged. It means that an instruction address can be directed, while an operand address cannot be directed.
As such, the following disadvantages are brought about when the address translation method is built in the computer system.
(1) The area used in the interrupt processing is limited.
If an interrupt occurs when a user refers to a virtual space using an access register, the OS starts to search for the cause of an interrupt for determining which kind of interrupt it is. Since the interrupt occurs at any time, it is impossible to specify a value of an access register at the time. Hence, if the interrupt-processing program tries to execute an instruction, the used access register is the register matching to the base register specified by the instruction and the used operand is a space indicated by the access register. Since the value of the matched access register cannot be specified, it is impossible to define which virtual space the operand for the instruction is to be read. It results in the interrupt-processing program being unable to execute the object processing. In order to avoid this disadvantage, the interrupt-processing program has to execute the processing using only the instruction which does not use the base register. Yet, the area to be accessed without the base register is 4096 bytes (area specified by a displacement portion of 12 bits included in an operand). The area capacity is insufficient for the interrupt processing.
(2) A lot of overheads are required for solving an address translation exception
When an address translation exception (page fault) interrupt occurs, it is necessary to allocate a real page to a virtual address at which a page fault occurs for completing address translation. When the page fault occurs in the virtual space related to the access register, it is necessary to obtain information used for identifying the virtual space, an identifier of an address space related to the access register, an address translation table address for the address space, a page register number on which the access register is related, and the like. With these pieces of information, the OS obtains an entry address for an address translation table matched to the virtual address at which a page fault occurs. The conventional hardware, however, merely saves the virtual address at which the page fault occurs at a specific address of the main storage. In order to obtain the foregoing pieces of information in accordance with the prior art, it is necessary to simulate address-calculating and address-translating process of an instruction which causes the page fault in accordance with the software and obtain a virtual address and a virtual space at which the page fault occurs. It results in entailing a lot of overhead.